Go to start of banner

# Introduction

This product note explains how to compute the control delay of a control algorithm implemented on B-Box RCP or B-Board PRO.

# Principles

The execution of a digital control algorithm inevitably introduces a delay along the control chain, which has an impact on the system response delay, and therefore achievable closed-loop control bandwidth.

This delay is key in the computation of controller parameters, such as $//$ and $//$ in the case of a PI current controller. Essentially, the control delay can be estimated as the sum of the sampling delay, cycle delay, modulation delay and signal propagation delay.

## 1) Sampling delay

In digital control, the analog to digital conversion (ADC) practically always corresponds to a zero-order hold (ZOH) that maintains the measurement during the sampling period $//$. This sample and hold operation introduces a lag of $//$ [1,2], which is the sampling delay:

## 2) Cycle delay

In the B-Box RCP/B-Board PRO, the execution of the control task starts directly at the end of the sampling process (i.e. after the ADC conversion). The modulation parameters (duty-cycle and carrier phase) are computed in the controller CPU and sent to the PWM generator (FPGA peripheral). The cycle delay is defined as the time between the sampling of the analog inputs and the end of the transfer of the newly computed modulation parameters to the FPGA.

With imperix controllers, the modulators are always latching their parameters (e.g. duty-cycle) at the beginning of the PWM period. The only exception is the carrier-based modulation (CB-PWM), which can be configured for double-rate update.

The calculation of the cycle delay must be determined in each specific case. The examples given below illustrate possible scenarios.

When a control algorithm is running on a B-Box RCP/B-Board PRO, the corresponding cycle delay can be found in the Timing info tab of BB Control:

## 3) Modulation delay

In most digital implementations of PWM generators, the duty-cycle is updated at each switching period when the carrier is equal to zero [2]. By default, this is also the case with B-Box RCP/B-Board PRO:

The equivalent model of the PWM generation process is shown below:

The update of the duty-cycle is analogous to a zero-order hold (ZOH) that maintains the value of the duty-cycle during the switching period $//$. This increases the response delay of the system. This delay is the time between the duty-cycle "sampling" instant and the instant when the resulting PWM state changes (when $//$ intersects with the carrier).

For example, in the case of a sawtooth carrier, the time delay is $//$, which means that the average time delay is $//$. For the inverted sawtooth, triangular and inverted triangular carriers, the average delay time is also $//$ [2].

In the case of a double-update rate (triangle and inverted triangle carriers), the duty-cycle is updated twice per switching period, namely at the two peaks of the carrier, resulting in a time delay of $//$. The double-update rate can give significant benefits in reducing the overall delay [2].

## 4) Propagation delay

The propagation delay from the controller to the power semiconductor (IGBT or MOSFET) should also be taken into account to determine the total time delay of the digital control.

The propagation delay can often be neglected for “slow” switching applications. However, the propagation delay may become significant in high switching frequency applications: for example, at hundreds of kHz: the propagation is typically several percent (sometimes tens of percent) of the overall delay. The propagation delay should, therefore, be taken into account for a better determination of the controller parameters.

# Examples

### Example 1

Sawtooth carrier, identical switching and sampling frequencies (single-update rate), sampling with a phase equal to 0, and a CPU load at 20%:

• Sampling delay: $//$;

• Cycle delay: $//$;

• PWM delay: $//$.

• Total time delay: $//$

In this case, the cycle delay is always $//$, independently of the CPU load.

### Example 2

Triangular carrier, identical switching and sampling frequencies (single-update rate), sampling with a phase equal to 0.5, and a CPU load at 60%.

• Sampling delay: $//$;

• Cycle delay: $//$;

• PWM delay: $//$.

• Total time delay: $//$

In this case, the effective cycle delay depends on the CPU load because the new PWM parameters would be applied only after $//$ in case the CPU load is below 50%.

This configuration is the only one that guarantees that the current measurement is made exactly in the middle of the switching ripple.

### Example 3

Triangular carrier, identical sampling switching frequencies, but double PWM update rate. Sampling with a phase equal to 0.5, and a CPU load at 60%.

• Sampling delay: $//$;

• Cycle delay: $//$;

• PWM delay: $//$ .

• Total time delay: $//$

### Example 4

Triangular carrier, sampling and update at twice the switching frequency, sampling with a phase equal to 0, and a CPU load at 70%.

• Sampling delay: $//$;

• Computation delay: $//$;

• PWM delay: $//$ .

• Total time delay: $//$

In this case, the effective cycle delay is independent of the CPU load.

[1] Gene F. Franklin, H. David Powell, and Michael L. Workman; “Digital Control of Dynamic Systems, Third Edition”; 1980

[2] S. Buso and P. Mattavelli; “Digital Control in Power Electronics”; 2006

• No labels