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# General description

The CONFIG block is mandatory and serves to:

• configure the main time base of the model (control task frequency)

This block also configures various model parameters and generates signals used in simulation. More information regarding the simulation is available in the following notes:

## Signal specification

• The first output is the PWM clock signal and can be connected to the > input of the PWM blocks to set their frequency to the CLK_0 frequency.

• The second output is the sampling signal and must be connected to the > input signal of all the ADC blocks of the model.

The simulation behavior of these signals is described in PN135: Simulation essentials with Simulink.

The CONFIG block embeds a CLK block to configure CLOCK_0. More information on the CLK block can be found in the related note: CLK - Clock generator.

• Clock frequency: sets the frequency of CLOCK_0, which is the time base for the ADC sampling, the control task execution, and the switching frequency of the connected PWM blocks.

• Sampling phase: sets the ADC sampling phase relative to CLOCK_0. The control task is executed right after the sampled values are available.

• Postscaler: divides the control task frequency such as $//$
The postscaler parameter has no impact on the sampling frequency.

• The oversampling parameter allows selecting from two methods of oversampling configuration; by selecting an oversampling ratio and having equidistant sample events (evenly distributed) or by explicitly defining each sampling event phase (vector of phases)

• The ADC acquisition delay can be set to:

• 2000 ns (compatible with the B-Box RCP and B-Board PRO)

• 500 ns (compatible with the B-Board PRO only)

It corresponds to the acquisition and conversion process time of the ADC chip. This parameter can take multiples values because the B-Box analog frontend ADC chips are not the same as the ones embedded in to B-Board PRO.

Further documentation on how to benefit from the oversampling option is available in PN154: Oversampling.

## Simulation parameters

The cycle delay represents the total control execution time. As such, this sums up the delays involved in the control dynamics (ADC acquisition, data read, control task execution, data write). It is used in simulation mode only and serves to accurately model the time at which the PWM parameters are actually updated. This is part of the total actuation delay, whose modelling is required in order to accurately simulate control dynamics.

This value can be expressed n seconds (s) or as a ratio relative to the CLOCK_0 period (Period).

As the cycle delay cannot be anticipated before the control code is run on the target, this parameter must be measured during run time. To this end, the BB Control utility provides the necessary information in the Timing info panel.

# PLECS block

## Signal specification

• The Task output must be connected to the Control Task Trigger block. The Control Task Trigger nominal base sample time must be equal to 1/Clock frequency.

• The PWM clock signal can be connected to the > input of the PWM blocks to set their frequency to the CLOCK_0 frequency.

• The ADC clock output is the sampling signal. It must be connected to the > input signal of all the ADC blocks of the model.

The CONFIG block embeds a CLK block to configure CLOCK_0. More information on the CLK block can be found in the related note: CLK - Clock generator.

• Clock frequency: sets the frequency of CLOCK_0, which is the time base for the ADC sampling, control task execution, and the switching frequency of the connected PWM blocks.

• Sampling phase: sets the ADC sampling phase relative to CLOCK_0. The control task is always executed right after the sampled values are available.

• Postscaler: divides the control task frequency such as $//$
The postscaler parameter has no impact on the sampling frequency.

• The oversampling parameter allows selecting from two methods of oversampling configuration; by selecting an oversampling ratio and having equidistant sample events (evenly distributed) or by explicitly defining each sampling event phase (vector of phases)

• The ADC acquisition delay can be set to:

• 2000 ns (compatible with the B-Box RCP and B-Board PRO)

• 500 ns (compatible with the B-Board PRO only)

It corresponds to the acquisition and conversion process time of the ADC chip. This parameter can take multiples values because the B-Box analog frontend ADC chips are not the same as the ones embedded in to B-Board PRO.

Further documentation on how to benefit from the oversampling option is available in PN154: Oversampling.

## Simulation

The cycle delay represents the total control execution time. As such, this sums up the delays involved in the control dynamics (ADC acquisition, data read, control task execution, data write). It is used in simulation mode only and serves to accurately model the time at which the PWM parameters are actually updated. This is part of the total actuation delay, whose modelling is required in order to accurately simulate control dynamics.

This value can be expressed n seconds (s) or as a ratio relative to the CLOCK_0 period (Period).

As the cycle delay cannot be anticipated before the control code is run on the target, this parameter must be measured during run time. To this end, the BB Control utility provides the necessary information in the Timing info panel.

# C++ functions

void ConfigureMainInterrupt(tUserSafe (*userCallback)(void), tClock clock,
float phase, unsigned int postscaler=0);

Configures the user control task routine.

### Parameters

• userCallback: pointer on the control task callback function that is called at each interrupt

• clock: defines the clock used to trigger the sampling and interrupt

• phase: sets the ADC sampling phase relative to CLOCK_0. The interrupt is executed right after the ADC acquisition ended.

• poscaler: divides the interrupt frequency such as $//$
The postscaler parameter has no impact on the sampling frequency.

The ADC sampling phase is set using the ConfigureMainInterrupt function. However, if oversampling is required, additional sampling instants can be configured using the ADC function Adc_AddSamplingEvent() documented in ADC - Analog data acquisition.

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