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# Introduction

DC bus voltage imbalance in an NPC inverter may overstress the capacitors and semiconductors of the converter. Besides, the output voltage and phase current may also be deteriorated. As such, maintaining adequate balancing is necessary at all times.

This technical note presents different ways to balance the DC bus voltage of a three-phase three-level NPC inverter.

A Simulink file with a control example for the B-Box RCP or B-Board PRO is provided, for both Carrier-Based and Space-Vector modulations. Experimental results obtained with the ACG SDK are shown.

# Causes of unbalanced voltage

Generally, the overall voltage of the DC-link is controlled by a cascaded control. However, the voltage of each half bus is not controlled individually.

Each phase can have three possible states:

• “P”, when the phase is clamped to $//$;

• “O”, when the phase is clamped to the midpoint of the DC bus;

• “N”, when the phase is clamped to $//$.

Consequently, a three-phase NPC inverter has 27 possible states that can be represented as vectors in the Clarke referential, as presented in TN135 :

These vectors can be divided into 4 groups according to their magnitude:

• zero vectors: 0

• small vectors: $//$

• medium vectors: $//$

• large vectors: $//$

The effect of each one of these vector groups is represented in the figure below. Zero and large vectors haven't any unbalancing effect. For medium vectors, the sign of the voltage variation is undefined. The small vectors are the ones that have the largest impact [1].

The current path determines if the DC bus capacitors are charging or discharging.

# DC bus balancing methods

In this technical note, two different methods are presented in order to balance to DC bus voltage of an NPC inverter: one for Carrier-Based modulation (CB-PWM), and the second for Space-Vector modulation (SV-PWM). Further details on modulation techniques are given in TN135.

## Carrier-based PWM

For carrier-based modulation, each of the two carriers is related to its corresponding half DC bus voltage. Therefore, if the amplitude of the carriers is changed to reflect the effective voltage, the utilization of the DC-link is changed [2]. This is shown in the picture below:

In practice, it is often easier to alter the value of the duty cycle rather than the amplitude of the triangular carrier. Therefore, the same result can be observed using the following formula:

With $//$ dependent on the sign of the phase current and defined as:

## Space vector PWM

As presented in TN135, SV-PWM requires that the two active vectors $//$ and $//$ that are the closest to $//$ are found, as well as a zero vector $//$. Then, the corresponding duty cycles $//$, $//$ and $//$ can be determined.

These vectors are then organized following a specific pattern in to reduce the number of commutations. Normally, the duty cycle $//$ is equally distributed between two new zero vectors $//$ and $//$. However, as vectors $//$ are always P-type small vectors, and vectors $//$ are always N-type vectors, it is possible to adjust the share between $//$ and $//$in order to influence the DC voltages balancing. This is the main principle governing the proposed balancing algorithm.

As such, the duty ratios are computed as:

[1] Kalpesh H. Bhalodi, Pramod Agrawal, “Space Vector Modulation with DC-Link Voltage Balancing Control for Three-Level Inverters”, in IEEE International Conference on Power Electronic, 2007.

[2] Wojciech Kołomyjski, “Modulation Strategies for Three-level PWM Converter-fed Induction Machine Drives”, thesis available on Warsaw University of Technology website, page 52, 2009.

# B-Box / B-Board implementation

The two figures below show the implementation in Simulink.

For the SV-PWM, the block provided in the imperix blockset takes the reference vector in the αβ0 coordinates and automatically computes the duty cycles for each phase. For the balancing of the DC bus, adding the same correction $//$ to the duty cycles of each phase is equivalent to adding an homopolar component to the reference vector $//$:

CB-PWM implementation

SV-PWM implementation

## Results

The DC bus balancing has been tested in the topology of a DC source connected to the grid through an NPC inverter.

In the initial condition, the DC bus is charged and unbalanced ($//$), and then the inverter starts to switch. The following graph shows the experimental result with the method for SV-PWM:

Independently of the method used for balancing the DC bus, the time for balancing the DC bus depends on the current reference of the inverter: the higher the current, the faster the DC bus balances.

The experimental result shown above is done with $//$and that’s why the balancing takes almost 1.5 seconds. With higher currents, the balancing lasts a few hundred milliseconds.

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